Is advanced packaging, more than wafer capacity, the real limit on AI chip supply?

Thesis

TSMC is where the AI hardware cycle turns into physical product. A GPU or custom accelerator is a logic die made on a leading-edge wafer, joined to stacks of high-bandwidth memory on a large interposer, then tested. TSMC does the first and third steps for most of the market and, through CoWoS, the second. Which step limits how many accelerators reach data centers, wafers or packaging, is the question that matters here.

Packaging has been the tightest step in 2026, but it is one limiter in a chain, and the chain is loosening unevenly. Wafer capacity is not short in aggregate. TSMC shipped about 15 million 12-inch equivalent wafers in 2025 against annual capacity that exceeded 17 million, so shipments ran at no more than about 88% of stated capacity. The shortage sits in specific places: TrendForce reports that 5/4nm and 3nm capacity was fully booked in the second quarter, and CoWoS has had a supply gap that institutional investors put at about 20% in June, with a forecast of about 10% by the end of 2026.

On its October call Chairman and CEO C.C. Wei said the gap between demand and supply is still quite big. He also acknowledged a back-end shortage and described work with GlobalFoundries on silicon interposers to add capacity, per the same transcript. A foundry that is also the packaging bottleneck can price both, and pricing evidence has started to appear: TrendForce reported on October 27 that TSMC is reportedly weighing CoWoS price increases of up to 20%.

Scarcity shows in the financials: gross margin of 66.4% in Q3 2026 against 59.9% for all of 2025. Packaging is a small share of revenue today, slightly over 10% in 2025, up from about 8% in 2024, and expected in the low teens in 2026 per the CFO, whose remark carries a correction added by the company after the call (some secondary coverage still reports the uncorrected 8% for 2025). It still decides when the rest of revenue converts to shipped systems. The binding constraint may also be moving, with memory a competing candidate: SK hynix said on October 28 that its DRAM and HBM supply is effectively sold out through 2029. If memory, not CoWoS, sets the pace by 2027, TSMC’s packaging build-out would matter less to industry unit volume, though not necessarily to TSMC’s own economics.

The ADR closed at US$406.13 on October 30. Margin dilution and capital intensity, covered under Financials and Valuation, are part of the debate around the shares.

Company History

TSMC was founded in 1987 as a joint venture among the Republic of China government and private investors and became a dedicated foundry, building chips only to customers’ designs. Its shares have been listed in Taipei since September 1994 and its ADSs on the New York Stock Exchange since October 1997. Each ADS represents five ordinary shares, which follows from the 20-F’s NT$65.47 diluted EPS per share and NT$327.34 per ADS.

The dedicated-foundry model let fabless companies skip fab ownership, and TSMC accumulated process leadership as those customers grew. The company now operates one 150mm fab, six 200mm fabs, nine 300mm fabs and seven advanced backend fabs. That last number is the packaging footprint: the company has built back-end capacity as a core business line, not an outsourced afterthought, and it markets it as 3DFabric, which includes CoWoS and SoIC.

Geographic expansion is the most recent chapter. The company has fabs in Arizona, Kumamoto in Japan, and a subsidiary building in Dresden, Germany, with up to US$6.6 billion in direct U.S. CHIPS Act funding and up to US$5 billion in proposed loans for the Arizona projects. In mid-July 2026 TSMC announced an additional US$100 billion Arizona investment, including advanced packaging facilities, according to TrendForce.

Leadership is stable. C.C. Wei is chairman and CEO and has 28 years with the company; Wendell Huang is CFO. The workforce reached 90,557 at the end of 2025, up from 83,825 a year earlier.

Product

TSMC sells manufacturing capacity measured in wafers, and since 2023 it has also sold assembly of those wafers into multi-die packages. Revenue is reported by process node and by customer platform.

Leading-edge logic (N2, N3, N5)

The newest nodes carry the AI business. In Q3 2026, wafer revenue split 8% 2nm, 33% 3nm, 28% 5nm and 10% 7nm, which puts nodes of 7nm and below at 79% of wafer revenue. Two nanometer is the new layer, and CFO Huang cited the steep ramp of 2nm in Q4.

The roadmap continues. On the October call management said annual N2-family capacity is expected to more than double in 2027, and that A14 reaches risk production in 2027 and volume production in 2028. Both statements come from the LSEG-edited call transcript that TSMC hosts on its investor site.

Leading-edge wafers also carry price. TrendForce reports TSMC plans 3% to 6% wafer-out price increases starting January 2027, varying by process node. Reports of price increases are not announcements; we treat them as directional.

Advanced packaging (CoWoS, SoIC, 3DFabric)

CoWoS places logic dies and HBM stacks on a silicon interposer, then onto a substrate. It exists because an AI accelerator needs memory bandwidth that ordinary board-level connections cannot supply. On the October call Wei said CoWoS remains the number one choice for customers and that TSMC is in production on 5X reticle-size packaging, with 9X and 14X in development. Larger interposers fit more compute and memory per package, but each size step raises the area of expensive silicon per unit and lowers how many units a wafer yields.

Economically the product is priced like an advanced node. TrendForce, citing Commercial Times, put CoWoS wafer ASP at about US$10,000, on par with 7nm. Advanced packaging margins sit below the corporate average today, according to the same report, which expects them to move toward leading-edge levels with scale.

The next form factor is panel-level. The CoPoS (chip on panel on substrate) pilot line had major equipment installed in February 2026, full line setup expected by June, and market expectations of mass production as early as 2028 to 2029. Nothing in CoPoS changes 2026 or 2027 supply.

Specialty and mature nodes

Smartphone, IoT, automotive and consumer platforms use a broader node range and some packaging (InFO for premium phones). These platforms matter for diversification more than for the bottleneck question. In Q3 2026 smartphone was 21% of revenue, automotive 4%, IoT 4% and digital consumer electronics 1%.

Market

Customer

Revenue is concentrated by customer and by region. The 20-F states that the ten largest customers accounted for 78% of 2025 net revenue, up from 70% in 2023. The largest customer fell to 19% of 2025 revenue from 25% in 2023 while the second largest rose to 17% from 11%. The filing does not name customers. The shift in rank order is consistent with a data-center customer overtaking a handset customer, but we cannot confirm identities from the filing.

By customer headquarters, North America was 75% of 2025 revenue (NT$2,875 billion), up from 68% in 2023. China was 9%, Japan 4%, and Europe, Middle East and Africa 3%.

By platform, high performance computing was 58% of 2025 revenue, or NT$2,193 billion, up 48%, and reached 68% in Q3 2026, up 22% sequentially. The mix shift is large enough that TSMC’s results now track AI capital spending more than handset cycles.

On the packaging side, the customer list is more concentrated than the wafer side. A January 2026 TipRanks article attributes to Morgan Stanley an NVIDIA share of about 60% of TSMC’s 2026 CoWoS capacity and reports Broadcom at about 15% and AMD at about 11% without naming a source for those two. These are analyst estimates and TSMC does not disclose allocation. If correct, three designers hold roughly 86% of the scarce step, which gives TSMC bargaining weight in allocation and gives those designers a reason to pre-commit.

Market Size

TSMC is the market for advanced logic, so its own revenue is the clearest sizing. Trailing revenue was NT$4.94 trillion for the four quarters ended September 2026, summing four reported quarters, against NT$3.81 trillion in calendar 2025. In dollars, management guides full-year 2026 growth of about 44%.

For the foundry industry, TrendForce estimates the top ten foundries generated nearly US$53.49 billion in Q2 2026, up 11.5% from the prior quarter. TSMC’s revenue was nearly US$40.2 billion, which TrendForce reports as a 72.5% share. The two dollar figures alone imply 75%, so TrendForce’s share base is not simply the top-ten total. Other firms define the market differently and report different shares, so we use TrendForce consistently.

For the AI accelerator market, management has guided a mid-to-high 50s percent compound annual growth rate for AI accelerator revenue over 2024 to 2029, a narrow definition of AI accelerators, and Wei said it will probably be higher. This is the number we would watch for revision.

Competition

Competitive Landscape

At the wafer level, competition for leading-edge AI logic is thin. TSMC’s 72.5% foundry share in Q2 2026 compares with 5.9% for Samsung and 5.4% for SMIC.

At the packaging level, the market is less closed. CoWoS is the standard for large AI packages, but alternatives exist, and management on the October call called its packaging very, very competitive, and TrendForce names Intel’s EMIB as the rival approach. Three outside sources of capacity matter: OSATs (outsourced assembly and test firms), Intel’s packaging business, and TSMC’s own overflow arrangements.

Institutional estimates reported by TrendForce suggest that non-TSMC players including ASE and Amkor will add capacity equal to 110,000 CoWoS wafers per month by the end of 2028, against TSMC’s own roughly 130,000 per month at the end of 2026 and 260,000 at the end of 2028. On those estimates, outside capacity would be about 30% of the 2028 total (110,000 of 370,000). That erodes TSMC’s packaging scarcity premium over time without removing TSMC from the process, because wafer bumping, interposer and some steps may still pass through TSMC.

Competitors

Samsung Foundry

Samsung combines a leading-edge logic foundry with an HBM memory business. Its foundry revenue was US$3.26 billion in Q2 2026, up 1.8% sequentially, and its share fell as competitors grew faster. Samsung’s relevance to the packaging question runs through memory: Herald reports signs that Samsung is narrowing the gap in HBM, in its coverage of SK hynix’s results. A stronger Samsung in HBM raises memory supply, which relieves a competing bottleneck.

Intel Foundry

Intel is pursuing the packaging gap with EMIB-T. Investor estimates reported by TrendForce put Intel’s CoWoS-equivalent capacity at 15,000 to 20,000 wafers per month in 2027 and 40,000 to 45,000 in 2028. These are small beside TSMC’s plan but not negligible at the margin if customers are allocation-constrained. We did not find a named external 14A wafer customer in sources we opened, so Intel’s wafer threat to TSMC remains unconfirmed.

ASE and Amkor (OSATs)

ASE raised 2026 capital expenditure by US$2 billion to US$10.5 billion, and its SPIL unit broke ground on a Douliu plant in August that is expected to introduce CoWoS. Amkor lifted planned Arizona phase-two investment from US$7 billion to US$12 billion and signed a 10-year advanced packaging and test agreement with TSMC in June. The Amkor deal is the more telling signal: TSMC is partnering with an OSAT in the U.S., not trying to absorb every step itself.

Business Model

TSMC earns revenue by selling wafers at negotiated prices and, for packaged parts, a packaging fee on top. Customers fund designs and masks; TSMC funds fabs, which is why capital intensity is the model’s defining feature. The 20-F records capital expenditures of NT$1,272 billion in 2025 against operating cash flow of NT$2,275 billion, leaving roughly NT$1.0 trillion before other investing items.

The model rewards utilization, and AI demand has delivered it at leading nodes. TSMC states that gross margin fluctuates with capacity utilization, price changes, cost improvement, product mix and exchange rates. For 2025 the 20-F attributed the revenue increase mainly to a higher ASP from advanced technology mix and to more wafer shipments, partly offset by a stronger NT dollar.

Currency matters because costs are largely in NT dollars and revenue largely in U.S. dollars. Q4 guidance assumes 31.8 NT dollars per U.S. dollar. Readers comparing figures should check units: this memo states NT$ or US$ for every amount, and the ADR price is in dollars.

Two structural cost items are worth naming. Overseas fabs dilute gross margin by closer to 2% for full-year 2026, widening to 3% to 4% in the next few years. And advanced packaging sits below the corporate average margin today per TrendForce, so a rising packaging share pulls on the blended margin until price increases take hold.

Packaging capital needs are non-trivial. On the January call, CFO Huang said about 10% to 20% of the then-planned US$52 billion to US$56 billion 2026 budget would go to advanced packaging, testing, mask making and others. The budget now stands at US$60 billion to US$64 billion, reiterated on the October call, and we do not have an updated split.

Financials

Q3 2026

Revenue for the quarter ended September 30, 2026 was NT$1,494.24 billion, or US$46.72 billion, up 50.9% year on year in NT dollars and 41.2% in U.S. dollars. The gap between the two growth rates reflects exchange rates. Sequential growth was 17.6% in NT dollars and 16.2% in U.S. dollars.

Gross margin was 66.4% and operating margin 58.7%. The CFO attributed the 130 basis point sequential decline in gross margin mainly to the 2nm ramp. Net income was NT$763.06 billion, up 68.7%, and diluted EPS was NT$29.43, or US$4.60 per ADS.

Capital expenditure in the quarter was about NT$443 billion, or US$13.8 billion. TSMC ended the quarter with cash and marketable securities of about NT$4 trillion, or US$126 billion.

Guidance

Q4 2026 revenue is guided to US$52.3 billion to US$54.3 billion, gross margin to 65% to 67% and operating margin to 56.5% to 58.5%. The midpoint of revenue is a 14% sequential increase. The full-year 2026 dollar growth target is about 44%.

Capital spending is the swing factor for free cash flow. The 2026 budget is US$60 billion to US$64 billion, and management expects 2026 to 2028 capex to be significantly higher than the prior three years without giving 2027 numbers. Wei said revenue growth should still outpace capex growth.

Annual trend

In 2025 net revenue was NT$3,809 billion, up 31.6% in NT dollars, or US$121.4 billion at the filing’s convenience rate of NT$31.37 per US$. Gross margin was 59.9% versus 56.1% in 2024, and operating margin was 50.8% versus 45.7%. Net income attributable to the parent was NT$1,697.6 billion, and wafer shipments were 15.0 million 12-inch equivalents versus 12.9 million.

Quarterly gross margin has moved up through the year: NT$651,987 million of gross profit on NT$1,046,090 million of revenue in Q4 2025, and NT$992,379 million on NT$1,494,243 million in Q3 2026, which computes to about 62.3% and 66.4%. We computed the first figure; the second matches the company’s reported margin.

The balance of risk in the financials sits in mix and cost. Margin guidance for Q4 has a midpoint of 66%, down about 40 basis points, driven by 2nm and overseas fabs.

Valuation

Our market value uses the ADR basis: the NYSE close of US$406.13 on October 30, 2026 times 25,932,524,521 common shares outstanding (the 20-F cover count at December 31, 2025) divided by five, since one ADS equals five common shares, or about 5.19 billion ADS. That gives about US$2.11 trillion. The Taiwan-listed shares trade at a discount to the ADR: they closed at NT$2,370 on October 30, which at NT$32.58 per US$ (the X-Rates rate for that day; the Federal Reserve H.10 release showed 32.54 on October 23) values the company at about US$1.89 trillion, roughly 10% below the ADR-based figure. StockAnalysis lists US$1.77 trillion on its statistics page and US$1.88 trillion on its market-cap page; we use neither.

We recompute the multiples from cited inputs. Diluted EPS for the four quarters to September 2026 was NT$18.72, NT$22.08, NT$27.25 and NT$29.43, a total of NT$97.48 per share or NT$487.40 per ADS, which is US$14.96 at NT$32.58. The ADR therefore trades at 27.2x trailing earnings (StockAnalysis lists US$14.94 and 27.2x). StockAnalysis’s forward multiple of 19.1x rests on analyst estimates it does not disclose and implies about US$21.30 of forward earnings per ADS (our arithmetic).

For enterprise value we subtract net cash of US$100.36 billion from the ADR-based value, giving about US$2.01 trillion. Trailing revenue of NT$4,944.8 billion and operating income of NT$2,866.0 billion (sums of four reported quarters on StockAnalysis) equal US$151.8 billion and US$88.0 billion at NT$32.58. Enterprise value is therefore 13.2x sales and 22.8x operating income. These apply one spot rate to results that TSMC translated at quarterly average rates, so they are approximations.

The multiple should be read against the capital cycle. The 2025 filing shows operating cash flow of NT$2.27 trillion and capex of NT$1.27 trillion, and the 2026 budget is US$60 billion to US$64 billion with higher spending guided after that. StockAnalysis lists 41.5x price to free cash flow on its US$1.77 trillion value, which implies trailing free cash flow of about US$42.7 billion (our arithmetic). The same cash flow against the ADR-based value gives about 49x, well above the earnings multiple, which captures the difference between reported profit and cash left after fab construction.

For reference, the ADR closed at US$439.51 on October 28 and US$431.81 on October 29.

We make no fair-value claim. The comparison that matters is whether the earnings base grows as guided: Q4 revenue of US$52.3 billion to US$54.3 billion would put the annualized run rate above US$210 billion, if sustained.

Key Opportunities

Pricing power across wafers and packaging

TrendForce reports that TSMC is considering CoWoS increases of up to 20% and wafer-out increases of 3% to 6% from January 2027. If realized, packaging margin would move toward the corporate average faster, and the packaging share of revenue, slightly over 10% in 2025 and expected in the low teens in 2026, would rise further. Equipment lead times have lengthened to 6 to 8 months from 3 to 6, which favors firms that ordered early.

The risk to this opportunity is that it is reported rather than announced, and that customers with allocation-constrained supply may accept increases that customers with alternatives will resist.

Packaging volume growth through 2028

On Goldman Sachs’s projection, CoWoS output rises from 1.275 million wafers in 2026 to 2.73 million in 2027 and 3.48 million in 2028. Sell-side projections are not company guidance, and the percentage increase in 2027 (114%) is a modeled output, not a commitment. Separately, TSMC forecast CoWoS capacity growth of more than 80% CAGR from 2022 to 2027, at its May symposium as reported by Reuters via TrendForce, which points the same way.

Demand broadening beyond GPUs

TrendForce notes demand is expanding from AI GPUs to server CPUs and custom ASICs. Wei cited agentic AI CPUs as a further driver of silicon demand, alongside the accelerator growth behind the stated mid-to-high 50s CAGR. More designers means more customers competing for the same capacity, which supports utilization.

Arizona and U.S. policy cover

The January trade agreement lowered the U.S. tariff on Taiwanese goods from 20% to 15% and gave chipmakers building in the United States tariff-free import allowances of up to 2.5 times their new capacity during the build-out phase, with separate lower duty treatment for chips. Building packaging in Arizona, with the first facility planned before 2029 also reduces dependence on packaging in Taiwan for U.S.-made wafers.

Key Risks

Customer concentration and in-sourcing

The top ten customers were 78% of 2025 revenue and, on packaging, three designers reportedly hold most of the capacity. A change in orders by any one of them moves TSMC’s results. Hyperscalers designing their own chips add diversification but also add bargaining power, and several have the scale to underwrite alternative packaging suppliers.

The bottleneck moves to memory or power

If HBM supply, not CoWoS, limits accelerator shipments, TSMC’s packaging build-out will outrun the pace of the systems it supports. SK hynix said customer orders exceed twice what it can supply and that the shortage will last through 2030. Under that outcome, TSMC still earns on the wafers it makes but under-utilizes packaging capacity it financed. Other physical limits include power supply, which the 20-F lists among constraints that could affect demand, and tools, which the CFO called tight.

Cost dilution and capital intensity

Gross margin fell 130 basis points sequentially and Q4 guidance implies a further decline at the midpoint. Overseas dilution of 2% rising to 3% to 4% and a capex budget of US$60 billion to US$64 billion with higher spending guided for 2027 and 2028 make the margin a question of mix and execution as well as demand. Wei also flagged that consumer and price-sensitive segments face rising component prices.

Geopolitics and trade policy

Production is concentrated in Taiwan, and the 20-F details risks from trade tensions, export controls and tariffs. It also discloses that the company has been cooperating with authorities’ requests for additional information regarding chips that may have been diverted to a restricted entity. On trade, the filing notes that the IEEPA tariffs were declared unlawful by a February 2026 Supreme Court ruling, and Section 232 chip tariffs remain a possible tool whose timing we cannot confirm. The January agreement’s quota of up to 2.5 times new capacity shows how tightly tariff relief is tied to U.S. construction.

Alternative packaging erodes the premium

OSAT and Intel capacity, estimated at 110,000 wafers per month by 2028 for non-TSMC players, would lessen scarcity. A packaging price increase of up to 20% invites customers to qualify second sources faster. The supply gap narrowing from 20% to 10% is already a sign that scarcity is being worked off.

What Would Prove Us Wrong

Our view is that packaging is the tightest step through 2026 and that scarcity is being priced into TSMC’s results. Four observations would contradict it.

1. Packaging is not the limiter. If TrendForce or TSMC commentary reports CoWoS supply and demand in balance (gap below 5%) by the end of Q1 2027, while HBM4 remains the allocation constraint at SK hynix, then packaging stopped being the binding step in the first half of 2027 and the thesis is wrong for the following year.
2. The pricing does not arrive. If TSMC’s Q1 2027 gross margin is below 65% and no CoWoS or wafer price increase is confirmed by management on the January 2027 call, the scarcity premium is not showing in margin. Q4 2026 guidance sets a floor of 65%.
3. Wafer capacity, not packaging, is the constraint. If management reports that leading-edge wafer starts, not back-end capacity, limit shipments in 2027, for example by reporting 3nm and 2nm utilization above 100% of planned output while CoWoS has idle capacity, the premise that packaging outranks wafers fails. An early test is whether the N2-family capacity more than doubles in 2027 as stated.
4. Outside capacity arrives faster. If non-TSMC CoWoS-equivalent capacity exceeds 50,000 wafers per month by the end of 2027 in company or TrendForce updates, against the 110,000 by end-2028 estimate, the premium compresses earlier than we assume.

Summary

TSMC reported third-quarter results on October 15, 2026: revenue of US$46.72 billion, gross margin of 66.4% and HPC at 68% of sales, with Q4 guided to US$52.3 billion to US$54.3 billion. It holds a 72.5% foundry share on TrendForce’s basis, says CoWoS remains the first choice of its customers, and is spending US$60 billion to US$64 billion in 2026 to widen both.

Packaging has been the most binding step for AI accelerators in 2026 but not the only one. Wafers at 5/4nm and 3nm are fully booked, HBM is sold out for years, and tools are tight. The CoWoS gap is forecast to narrow from about 20% to about 10% by year-end, and outside capacity is scheduled to arrive between 2027 and 2028. TSMC participates in each constraint, so its pricing power does not depend on which step wins, though the value of its packaging build-out does.

As of October 30, 2026 the ADR trades at 27.2x trailing earnings on our calculation, on a market value of about US$2.11 trillion. The evidence that would change our view is listed under What Would Prove Us Wrong: a balanced CoWoS market by early 2027, a Q1 2027 gross margin below 65%, or faster outside packaging capacity.